# Machine Learning for Electronic Design Automation: A Survey

**Authors:** Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong, Xuefei Ning, Yuzhe Ma, Haoyu Yang, Bei Yu, Huazhong Yang, Yu Wang  
**arXiv:** [2102.03357](https://arxiv.org/abs/2102.03357)  
**Date:** 2021-01-10  
**Summary page:** https://www.summarizepaper.com/en/arxiv-id/2102.03357v2/

## Key points

- Complexity of VLSI design is increasing due to down-scaling of CMOS technology
- Machine learning (ML) techniques have been explored in EDA since the 1990s
- Recent breakthroughs in ML and growing complexity of EDA tasks have renewed interest in incorporating ML
- "Machine Learning for Electronic Design Automation: A Survey" provides a comprehensive review of existing ML studies for EDA
- ML can be applied at different levels of the EDA hierarchy, including circuit synthesis and optimization, physical design automation, timing analysis and verification, functional verification, fault diagnosis and yield optimization
- The paper offers valuable insights into how ML techniques can address the increasing complexity of VLSI design
- Serves as a valuable resource for researchers and practitioners in the field.

## Summary

In the field of electronic design automation (EDA), the complexity of very large-scale integrated (VLSI) design is increasing due to the down-scaling of CMOS technology. To address this challenge, researchers have been exploring the application of machine learning (ML) techniques in EDA since the 1990s. However, recent breakthroughs in ML and the growing complexity of EDA tasks have sparked renewed interest in incorporating ML to solve these challenges. In their paper titled "Machine Learning for Electronic Design Automation: A Survey," authors Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong, Xuefei Ning, Yuzhe Ma, Haoyu Yang, Bei Yu, Huazhong Yang and Yu Wang present a comprehensive review of existing ML studies for EDA. The authors organize their review following the EDA hierarchy and highlight that with advancements in CMOS technology leading to smaller feature sizes and increased transistor densities on chips traditional design methodologies face significant challenges. This necessitates exploring new approaches such as ML to improve various aspects of EDA tasks. The paper discusses how ML techniques can be applied at different levels of the EDA hierarchy including circuit synthesis and optimization by automating design space exploration and improving power consumption efficiency; physical design automation by optimizing placement and routing algorithms for improved performance; timing analysis and verification tasks by identifying critical paths and estimating timing delays accurately; functional verification by automating test generation and accelerating simulation processes; fault diagnosis and yield optimization by detecting faults in integrated circuits to improve reliability as well as optimizing manufacturing processes to enhance chip yield and reduce costs. Overall this survey paper provides a comprehensive overview of existing research on ML for EDA organized based on the EDA hierarchy offering valuable insights into how ML techniques can be effectively applied to address the increasing complexity of VLSI design. This work serves as a valuable resource for researchers and practitioners in the field guiding future developments and advancements in ML-based EDA methodologies.