# A Survey on RISC-V Security: Hardware and Architecture

**Authors:** Tao Lu  
**arXiv:** [2107.04175](https://arxiv.org/abs/2107.04175)  
**Date:** 2021-07-09  
**Summary page:** https://www.summarizepaper.com/en/paper/2107.04175v1/

## Key points

- The Internet of Things (IoT) has led to a technological revolution with embedded processors as the backbone for smart IoT devices.
- RISC-V ISA standard has gained significant traction in recent years, becoming a mainstream choice over Arm ISA for processors in IoT devices.
- Data security and user privacy are key challenges faced by IoT devices.
- The RISC-V community is actively exploring security solutions focused on establishing a root of trust (RoT) and safeguarding sensitive information from tampering or leakage.
- There is a lack of comprehensive surveys on existing security solutions within the academic community for RISC-V technology.
- The paper discusses representative security mechanisms used in RISC-V hardware and architecture, highlighting current practices and future directions for enhancing RISC-V security.

## Summary

The Internet of Things (IoT) has sparked a technological revolution, with embedded processors serving as the backbone for smart IoT devices. Traditionally, these processors were predominantly based on the Arm instruction set architecture (ISA). However, in recent years, the RISC-V ISA standard has gained significant traction in both industry and academia, emerging as the new mainstream choice. One of the key challenges faced by IoT devices is ensuring data security and protecting user privacy. To address potential security threats, the RISC-V community has been actively exploring security solutions focused on establishing a root of trust (RoT) and safeguarding sensitive information from tampering or leakage. While numerous RISC-V security research projects are currently underway, there remains a lack of comprehensive surveys on existing security solutions within the academic community. The paper delves into representative security mechanisms employed in RISC-V hardware and architecture, shedding light on current practices and future directions for enhancing RISC-V security. By offering insights into potential research avenues and development strategies, this survey aims to inspire researchers and developers working within the realm of RISC-V technology.