# HP-GNN: Generating High Throughput GNN Training Implementation on CPU-FPGA Heterogeneous Platform

**Authors:** Yi-Chien Lin, Bingyi Zhang, Viktor Prasanna  
**arXiv:** [2112.11684](https://arxiv.org/abs/2112.11684)  
**Date:** 2021-12-22  
**Summary page:** https://www.summarizepaper.com/en/paper/2112.11684v1/

## Key points

- Graph Neural Networks (GNNs) are powerful tools with applications in recommendation systems, molecular property prediction, traffic forecasting, and more.
- Researchers are optimizing GNN training on CPU-FPGA platforms for enhanced efficiency and speed.
- HP-GNN is a cutting-edge framework designed to automatically generate high throughput GNN training implementations on a specified CPU-FPGA platform.
- Key components of HP-GNN include optimized data layout, specialized hardware templates, design space exploration engine, and high-level APIs for minimal code input.
- HP-GNN experiments showed remarkable performance gains with average speedups of $55.67\times$ compared to CPU-only setups and $2.17\times$ compared to CPU-GPU configurations.
- When benchmarked against existing implementations, HP-GNN demonstrated speedups of up to $4.45\times$, highlighting its effectiveness in accelerating GNN training processes.

## Summary

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In the realm of machine learning, Graph Neural Networks (GNNs) have emerged as powerful tools with applications spanning recommendation systems, molecular property prediction, traffic forecasting, and more. To further enhance the efficiency and speed of GNN training, researchers have turned to CPU-FPGA heterogeneous platforms, leveraging the customizable data paths and abundant on-chip memory resources offered by FPGAs. However, optimizing and deploying GNN training on such platforms necessitates a deep understanding of hardware design and significant development efforts. In response to this challenge, a team of researchers comprising Yi-Chien Lin, Bingyi Zhang, and Viktor Prasanna introduces HP-GNN—a cutting-edge framework designed to automatically generate high throughput GNN training implementations on a specified CPU-FPGA platform. By taking GNN training algorithms and models as inputs, HP-GNN seamlessly performs hardware mapping onto the target platform. The framework is built upon several key components: optimized data layout and internal representation to reduce memory traffic and random accesses; specialized hardware templates supporting various GNN models; a design space exploration engine for automatic hardware mapping; and high-level application programming interfaces (APIs) enabling users to specify GNN training with minimal code input. To validate the efficacy of HP-GNN, the researchers conducted experiments using two popular sampling-based GNN training algorithms alongside two distinct GNN models. Across each algorithm-model combination tested, HP-GNN generated implementations on a state-of-the-art CPU-FPGA platform that exhibited remarkable performance gains. In comparison to CPU-only setups and CPU-GPU configurations, the generated implementations achieved average speedups of $55.67\times$ and $2.17\times$, respectively. Furthermore, when benchmarked against existing state-of-the-art GNN training implementations, HP-GNN demonstrated speedups of up to $4.45\times$, underscoring its effectiveness in accelerating GNN training processes. Overall, HP-GNN stands out as an innovative solution poised to benefit both application developers seeking enhanced performance in their machine learning tasks and researchers exploring novel advancements in the field of Graph Neural Networks.