# LPYOLO: Low Precision YOLO for Face Detection on FPGA

**Authors:** Bestami Günay, Sefa Burak Okcu, Hasan Şakir Bilge  
**arXiv:** [2207.10482](https://arxiv.org/abs/2207.10482)  
**Date:** 2022-07-21  
**Summary page:** https://www.summarizepaper.com/en/paper/2207.10482v1/

## Key points

- Significant advancements in edge computing devices and artificial intelligence applications
- Edge computing involves moving decision-making processes and computations to edge devices
- Field-Programmable Gate Arrays (FPGAs) are suitable for running Convolutional Neural Networks (CNNs)
- Face detection on surveillance systems is a highly anticipated application in the security market
- Researchers focused on redesigning and deploying the TinyYolov3 architecture for face detection
- PYNQ-Z2 was selected as the target board, featuring a low-end Xilinx Zynq 7020 SoC
- Redesigned TinyYolov3 model defined using various bit width precisions with the Brevitas library
- Model trained using the WiderFace dataset in a quantized structure
- On-chip memory of FPGA used to store all network parameters, last activation function modified
- High degree of parallelism applied to logical resources of FPGA
- Model converted into an HLS-based application using FINN framework and FINN-HLS library
- CPU of SoC utilized with multithreading mechanism for preprocessing, postprocessing, and TCP/IP streaming operations
- System achieved 2.4 Watts power consumption, 18 FPS throughput rate, and 0.757 mAP accuracy rate with a 4-bit precision model

## Summary

In recent years, there has been a significant advancement in edge computing devices and artificial intelligence applications. Edge computing involves moving decision-making processes and computations from servers to edge devices, requiring cheap and low-power devices. Field-Programmable Gate Arrays (FPGAs) are particularly suitable for running Convolutional Neural Networks (CNNs), which are the fundamental unit of an AI application, as they offer low power consumption and are capable of parallel operations. One highly anticipated application in the security market is face detection on surveillance systems. In this study, the researchers focused on redesigning and deploying the TinyYolov3 architecture for face detection. TinyYolov3 is a CNN-based object detection method specifically developed for embedded systems. The researchers selected the PYNQ-Z2 as their target board, which features a low-end Xilinx Zynq 7020 System-on-Chip (SoC). They defined the redesigned TinyYolov3 model in various bit width precisions using the Brevitas library, which allows for integer quantization of fundamental CNN layers and activations. The model was then trained using the WiderFace dataset in a quantized structure. To reduce latency and power consumption, the researchers configured the on-chip memory of the FPGA to store all network parameters. They also modified the last activation function to use rescaled HardTanh instead of Sigmoid. Additionally, they applied a high degree of parallelism to logical resources of the FPGA. The model was converted into an HLS-based application using the FINN framework and FINN-HLS library, which includes layer definitions in C++. After synthesis and deployment, the CPU of the SoC was utilized with a multithreading mechanism to handle preprocessing, postprocessing, and TCP/IP streaming operations. The results showed that with a 4-bit precision model, the system achieved a total board power consumption of 2.4 Watts, an 18 Frames-Per-Second (FPS) throughput rate, and a 0.757 mAP accuracy rate on Easy category images from WiderFace dataset. In conclusion, this study successfully redesigned and deployed TinyYolov3 architecture for face detection on PYNQ-Z2 FPGA board with efficient edge computing capabilities resulting in high performance with reduced latency and power consumption.