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Prototype of a Batched Quantum Circuit Simulator for the Vector Engine

Keichi Takahashi (Tohoku University), Toshio Mōri (RIKEN, The University of Osaka), Hiroyuki Takizawa (Tohoku University)

International Conference for High Performance Computing, Networking, Storage and Analysis (SC)
DOI: 10.1145/3624062.3624226 (Computer Science)
License: CC BY

Abstract: State-of-the-art quantum circuit simulators have mostly focused on scaling the number of qubits. However, we argue that studying current noisy quantum computers and variational quantum algorithms benefits from high-throughput simulation of intermediate-scale quantum circuits. We present the first implementation and evaluation of a batched quantum simulator on the NEC Vector Engine (VE), a vector processor with massive memory bandwidth that is ideal for memory-intensive state vector simulation. To take advantage of the long-vector architecture of VE, we design a parallelization strategy and memory layout suited for batched state vector simulation. Our evaluation shows that the latest-generation VE Type 30A achieves equal performance as the NVIDIA A100 80 GB model for single-qubit gates, but slightly underperforms A100 for two-qubit gates. Furthermore, our vector-friendly noise gate implementation offers a large speedup compared to that of cuStateVec. When simulating a noisy 16-qubit random circuit with our simulator, VE30 is up to 1.95 × faster than A100.

Published on 10 Nov. 2023